1. Field of the Invention
The present invention relates to prototyping electronic circuits. More particularly, the present invention relates to a method for prototyping asynchronous circuits using synchronous devices.
2. Related Art
Digital circuit designers use a wide variety of tools and techniques to prototype circuits so that the circuit design can be evaluated prior to committing the circuits to a custom integrated circuit device. Among the prototyping devices used by digital circuit designers are field-programmable gate-arrays and standard cell gate-array devices.
Both field-programmable gate-arrays and standard cell gate-array devices are optimized for prototyping synchronous, or clocked, digital circuits. A typical logic element of these devices is a master-slave D-type flip-flop, which is clocked by a globally distributed clock signal. In use, the digital circuit designer couples these logic elements together through primitive logic elements such as and-gates and or-gates to implement a desired circuit configuration. Manufacturers of these prototyping devices provide tools for the digital designer that simplify the task of mapping the designed circuit into the prototyping device. These tools assist the circuit designer in mapping a circuit configuration onto the prototype device. The tools also have internal processes, which aid in minimizing delays on interconnecting wiring and for checking for timing constraint violations.
There are, however, no equivalent devices and tools optimized for prototyping asynchronous, or unclocked, digital circuits. This leads designers of these asynchronous digital circuits to create a complete custom integrated circuit device, fabricate the device, and test the resulting device during the prototyping phase. The process of designing a custom integrated circuit device is a time-consuming manual process because of the lack of tools to aid this process. In addition, creating a custom integrated circuit device is a lengthy and expensive process leading to long delays for the designer trying to create a working asynchronous circuit.
In an attempt to overcome the drawbacks in prototyping asynchronous circuits, designers have attempted to map the circuits onto field-programmable gate-arrays using the available primitive logic elements to create the desired asynchronous circuit cells, such as set-reset (SR) flip-flops. Many asynchronous circuit cells rely on carefully managed delay constraints within the cells, while using more robust delay-tolerant or delay-insensitive communication techniques between the cells. Mapping such asynchronous cells onto standard cell gate-arrays and field-programmable gate-arrays has met with little success because the associated design tools expect the use of a clock signal that is not used in the asynchronous circuits. Furthermore, these design tools do not provide the designer with enough control over delays within the cell to ensure correct operation. These design tools often have sophisticated features that optimize logic between clocked storage elements, that because of the lack of the clock, asynchronous designs cannot take advantage of these features. When presented with an asynchronous design, these optimization tools usually make the circuit performance worse rather than better. Additionally, the resulting circuits do not use the resources of the field-programmable gate-array very efficiently because the primary storage elements available, such as master-slave D-type flip-flops that are normally operated by the globally distributed clock, cannot be used in the asynchronous cells.
Other techniques for prototyping asynchronous circuits using gate-arrays and/or field-programmable gate-arrays use completely different signaling protocols and circuit implementations in the clocked semi-custom gate-array technology than are used in the asynchronous full-custom design. The two designs are equivalent in function only and so an important feature of prototyping is lost, namely that the prototype circuit, built in some rapid turn-around technology, should resemble as much as possible the final circuit design to be implemented in full-custom technology.
What is needed is a method of mapping an asynchronous circuit design onto a field-programmable gate-array or a standard cell device, which eliminates the problems described above.
One embodiment of the present invention provides a system that facilitates prototyping asynchronous circuits where only a minimum of modifications are made to the circuit. The system first receives a design of an asynchronous circuit, which includes asynchronous cells. The system maps the asynchronous cells of the asynchronous circuit onto clocked synchronous cells within a logic array or programmable logic array device such as standard-cell gate-arrays and field-programmable gate-arrays. The mapping delays the generation of all asynchronous control events until the next clock event, thus preserving the full functionality of the asynchronous circuit. The system then programs the programmable synchronous device to perform the functions that are mapped from the asynchronous circuit. Finally, the system operates the programmable synchronous device, and the results of operating the programmable synchronous device are used to verify the design of the asynchronous circuit.
In one embodiment of the present invention, the programmable synchronous device includes a field-programmable gate-array.
In one embodiment of the present invention, the synchronous cell is taken from a standard cell library. A standard cell library is typically available in all forms of clocked semi-custom and custom integrated circuit design methods.
In one embodiment of the present invention, the system maps an asynchronous cell to a synchronous cell by first mapping an SR flip-flop in a control path of the asynchronous cell to a clocked D-type master-slave flip-flop in the synchronous device. Next, the system maps a latch, a pass-gate, and a sticky-buffer combination in a data path of the asynchronous cell to another clocked D-type master-slave flip-flop in the synchronous device. The clocked D-type master-slave flip-flop in the control path indicates whether the clocked D-type master-slave flip-flop in the data path is empty or full, i.e., whether the data stored in the D-type master-slave flip-flop in the data path is non-valid or valid. The system maps a gated clock to the clocked D-type master-slave flip-flop in the control path. The system also maps a gated clock to the clocked D-type master-slave flip-flop in the data path.
In one embodiment of the present invention, the system passes the gated clock to the clocked D-type master-slave flip-flop in the control path when the clocked D-type master-slave flip-flop in the control path is set to empty and an input signal indicates that incoming data are valid, thereby changing the state of the clocked D-type master-slave flip-flop in the control path to full. The system also passes this gated clock to the clocked D-type master-slave flip-flop in the control path when the clocked D-type master-slave flip-flop in the control path is set to full and an input signal from the next synchronous cell indicates that a next synchronous cell is empty, thereby setting clocked D-type master-slave flip-flop in the control path to empty. The system passes the gated clock to the clocked D-type master-slave flip-flop in the data path when the clocked D-type master-slave flip-flop in the control path is set to empty and the input signal indicates that incoming data are valid, thereby latching the incoming data in the clocked D-type master-slave flip-flop in the data path.
In one embodiment of the present invention, the system maps an SR flip-flop in a control path of the asynchronous cell to a data recirculation flip-flop in the control path of the synchronous cell. The system also maps a latch, a pass-gate, and a sticky-buffer combination in a data path of the asynchronous cell to another data recirculation flip-flop in the data path of the synchronous cell. The state of the data recirculation flip-flop in the control path indicates whether the data recirculation flip-flop in the data path is empty or full. The system maps a recirculation control signal to the data recirculation flip-flop in the control path. The system also maps a recirculation control signal to the data recirculation flip-flop in the data path.
In one embodiment of the present invention, the system sets the recirculation control signal applied to the data recirculation flip-flop in the control path to change a state of this data recirculation flip-flop when the data recirculation flip-flop is set to empty and the input signal indicates that incoming data are valid. The system also sets the recirculation control signal applied to the data recirculation flip-flop in the control path to change the state of this data recirculation flip-flop when the data recirculation flip-flop is set to full and an input signal indicates that a next synchronous cell is empty. The system sets the recirculation control signal applied to the data recirculation flip-flop in the data path to allow the incoming data value to set the state of the data recirculation flip-flop in the data path when the data recirculation flip-flop in the control path is set to empty and the input signal indicates that incoming data are valid.
In one embodiment of the present invention, the system maps an SR flip-flop in a control path of the asynchronous cell to a data recirculation cell in the control path of the synchronous cell. In this embodiment, the data recirculation cell in the control path includes an additional clocked D-type master-slave flip-flop to extend the data recirculation control signal. The system maps a pass-gate and a sticky-buffer in a data path of the asynchronous cell to a data recirculation flip-flop in the data path of the synchronous cell. The data recirculation cell in the control path indicates whether the data recirculation flip-flop in the data path is empty or full. The system maps a recirculation control signal to the data recirculation cell in the control path. The system also maps a recirculation control signal to the data recirculation flip-flop in the data path.
In one embodiment of the present invention, the system sets the recirculation control signal applied to the data recirculation cell in the control path to change a state of this data recirculation cell when the data recirculation cell is set to empty and an input signal indicates that incoming data are valid. The system also sets this recirculation control signal to change the state of the data recirculation cell when the data recirculation cell is set to full and another input signal indicates that a next synchronous cell is empty. The system sets the recirculation control signal applied to the data recirculation flip-flop in the data path to allow the incoming data value to set the state of the data recirculation flip-flop.